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fixup
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eckter committed Jan 15, 2025
1 parent 103acf2 commit ba916ae
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Showing 5 changed files with 16 additions and 8 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -418,7 +418,7 @@ fun parseRjsElectrification(
previousElectrification.value != electrification.voltage &&
previousElectrification.value != ""
) {
electrificationConflictAggregator.logError(
electrificationConflictAggregator.registerError(
"Electrification conflict on track-range ${electrificationRange.trackSectionID}" +
"[${previousElectrification.lower + chunk.offset.distance}, " +
"${previousElectrification.upper + chunk.offset.distance}]: " +
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Original file line number Diff line number Diff line change
Expand Up @@ -218,7 +218,7 @@ private fun getInitPartialBlocks(
val isBufferStop = rawSignalingInfra.isBufferStop(entryDet.value)
if (entrySignals == null) {
if (!isBufferStop)
missingSignalLogAggregator.logError(
missingSignalLogAggregator.registerError(
"no signal at non buffer stop ${rawSignalingInfra.getDetectorName(entryDet.value)}:${entryDet.direction}"
)
initialBlocks.add(
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Original file line number Diff line number Diff line change
Expand Up @@ -122,14 +122,14 @@ class SignalingSimulatorImpl(override val sigModuleManager: SigSystemManager) :
val entrySignal = rawSignalingInfra.getLogicalSignalName(signals[0])
val exitSignal =
rawSignalingInfra.getLogicalSignalName(signals[signals.size - 1])
blockLogAggregator.logError(
blockLogAggregator.registerError(
"error in block from $entrySignal to $exitSignal: $errorType"
)
}

override fun reportSignal(sigIndex: Int, errorType: String) {
val signal = rawSignalingInfra.getLogicalSignalName(signals[sigIndex])
signalLogAggregator.logError("error at signal $signal: $errorType")
signalLogAggregator.registerError("error at signal $signal: $errorType")
}
}
sigModuleManager.checkSignalingSystemBlock(reporter, sigSystem, sigBlock)
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ data class LogAggregator(
private var savedErrors = mutableListOf<String>()

/** Registers an error. Does not log anything before the `reportSummary` call. */
fun logError(msg: String) {
fun registerError(msg: String) {
nErrors++
if (savedErrors.size < maxReportedErrors) savedErrors.add(msg)
}
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14 changes: 11 additions & 3 deletions core/src/main/kotlin/fr/sncf/osrd/api/api_v2/RequirementsParser.kt
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ import fr.sncf.osrd.api.api_v2.conflicts.WorkSchedulesRequest
import fr.sncf.osrd.conflicts.*
import fr.sncf.osrd.sim_infra.api.RawSignalingInfra
import fr.sncf.osrd.standalone_sim.result.ResultTrain
import fr.sncf.osrd.utils.LogAggregator
import fr.sncf.osrd.utils.units.Duration
import fr.sncf.osrd.utils.units.TimeDelta
import fr.sncf.osrd.utils.units.seconds
Expand Down Expand Up @@ -99,9 +100,12 @@ fun convertWorkScheduleMap(
timeToAdd: TimeDelta = 0.seconds
): Collection<Requirements> {
val res = mutableListOf<Requirements>()
val logAggregator = LogAggregator({ requirementsParserLogger.warn(it) })
for (entry in workSchedules) {
val workScheduleRequirements = mutableListOf<ResultTrain.SpacingRequirement>()
workScheduleRequirements.addAll(convertWorkSchedule(rawInfra, entry.value, timeToAdd))
workScheduleRequirements.addAll(
convertWorkSchedule(rawInfra, entry.value, timeToAdd, logAggregator)
)
res.add(
Requirements(
RequirementId(entry.key, RequirementType.WORK_SCHEDULE),
Expand All @@ -122,9 +126,12 @@ fun convertWorkScheduleCollection(
workSchedules: Collection<WorkSchedule>,
timeToAdd: TimeDelta = 0.seconds,
): Requirements {
val logAggregator = LogAggregator({ requirementsParserLogger.warn(it) })
val workSchedulesRequirements = mutableListOf<ResultTrain.SpacingRequirement>()
for (workSchedule in workSchedules) {
workSchedulesRequirements.addAll(convertWorkSchedule(rawInfra, workSchedule, timeToAdd))
workSchedulesRequirements.addAll(
convertWorkSchedule(rawInfra, workSchedule, timeToAdd, logAggregator)
)
}
return Requirements(
RequirementId(DEFAULT_WORK_SCHEDULE_ID, RequirementType.WORK_SCHEDULE),
Expand All @@ -137,6 +144,7 @@ private fun convertWorkSchedule(
rawInfra: RawSignalingInfra,
workSchedule: WorkSchedule,
timeToAdd: TimeDelta = 0.seconds,
logAggregator: LogAggregator,
): Collection<ResultTrain.SpacingRequirement> {
val res = mutableListOf<ResultTrain.SpacingRequirement>()

Expand Down Expand Up @@ -181,7 +189,7 @@ private fun convertWorkSchedule(
"${tracksNotCoveredByRoutes.size} track sections were not fully covered by routes (ignoring some work schedules): " +
tracksNotCoveredByRoutes.take(3).joinToString(", ") +
(if (tracksNotCoveredByRoutes.size > 3) ", ..." else "")
requirementsParserLogger.warn(msg)
logAggregator.registerError(msg)
}
return res
}

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