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core: add warning on route ending on non route delimiting signal in block generation #10426

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Original file line number Diff line number Diff line change
Expand Up @@ -94,6 +94,7 @@ interface SignalingSystemDriver {
val stateSchema: SigStateSchema
val settingsSchema: SigSettingsSchema
val isBlockDelimiterExpr: String
val isRouteDelimiterExpr: String

fun checkBlock(reporter: BlockDiagReporter, block: SigBlock)

Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ internal fun internalBuildBlocks(
val signalDelimiters = findSignalDelimiters(rawSignalingInfra, loadedSignalInfra)
val detectorEntrySignals = makeDetectorEntrySignals(loadedSignalInfra, signalDelimiters)
val missingSignalLogAggregator = LogAggregator({ logger.debug(it) })
val nonRouteDelimitingSignalLogAggregator = LogAggregator({ logger.debug(it) })
val result =
blockInfraBuilder(loadedSignalInfra, rawSignalingInfra) {
// Step 2) iterate on zone paths along the route path.
Expand Down Expand Up @@ -96,9 +97,24 @@ internal fun internalBuildBlocks(
curBlock.signalPositions
)
}

// Finally we want to emit a warning if the route ends on a non route delimiting
// signal
if (!routeEndsAtBufferStop) {
warnOnRouteEndingOnNonRouteDelimitingSignal(
route,
routeExitDet,
detectorEntrySignals,
sigModuleManager,
rawSignalingInfra,
loadedSignalInfra,
nonRouteDelimitingSignalLogAggregator
)
}
}
}
missingSignalLogAggregator.logAggregatedSummary()
nonRouteDelimitingSignalLogAggregator.logAggregatedSummary()
return result
}

Expand Down Expand Up @@ -334,3 +350,27 @@ private fun BlockInfraBuilder.updatePartialBlocks(
}
return nextBlocks
}

private fun warnOnRouteEndingOnNonRouteDelimitingSignal(
route: RouteId,
routeExitDet: DirDetectorId,
detectorSignals: IdxMap<DirDetectorId, IdxMap<SignalingSystemId, AssociatedSignal>>,
sigModuleManager: InfraSigSystemManager,
rawSignalingInfra: RawSignalingInfra,
loadedSignalInfra: LoadedSignalInfra,
logAggregator: LogAggregator
) {
val endSignals = detectorSignals[routeExitDet] ?: return
for (associatedSignal in endSignals.values()) {
val logicalSignalId = associatedSignal.signal
val signalingSystem = loadedSignalInfra.getSignalingSystem(logicalSignalId)
val sigSettings = loadedSignalInfra.getSettings(logicalSignalId)
val routeEndsWithRouteEndingSignal =
sigModuleManager.isRouteDelimiter(signalingSystem, sigSettings)
if (!routeEndsWithRouteEndingSignal) {
logAggregator.registerError(
"Route ${rawSignalingInfra.getRouteName(route)} ends with non-route delimiting signal on signaling system ${signalingSystem}"
)
}
}
}
Original file line number Diff line number Diff line change
Expand Up @@ -90,4 +90,8 @@ class MockSigSystemManager(
override fun isBlockDelimiter(sigSystem: SignalingSystemId, settings: SigSettings): Boolean {
return true
}

override fun isRouteDelimiter(sigSystem: SignalingSystemId, settings: SigSettings): Boolean {
return true
}
}
Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,10 @@ class SigSystemManagerImpl : SigSystemManager {
return evalSigSettings(sigSystemPool[sigSystem].isBlockDelimiterExpr, settings)
}

override fun isRouteDelimiter(sigSystem: SignalingSystemId, settings: SigSettings): Boolean {
return evalSigSettings(sigSystemPool[sigSystem].isRouteDelimiterExpr, settings)
}

override fun checkSignalingSystemBlock(
reporter: BlockDiagReporter,
sigSystem: SignalingSystemId,
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -57,6 +57,8 @@ interface InfraSigSystemManager {
fun getOutputSignalingSystem(driver: SignalDriverId): SignalingSystemId

fun isBlockDelimiter(sigSystem: SignalingSystemId, settings: SigSettings): Boolean

fun isRouteDelimiter(sigSystem: SignalingSystemId, settings: SigSettings): Boolean
}

interface LoadedSignalInfra {
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@ object BAL : SignalingSystemDriver {
override val settingsSchema = SigSettingsSchema { flag("Nf") }
override val parametersSchema = SigParametersSchema { flag("jaune_cli") }
override val isBlockDelimiterExpr = "true"
override val isRouteDelimiterExpr = "Nf"

override fun checkBlock(reporter: BlockDiagReporter, block: SigBlock) {
// Check that we have the correct number of signals
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@ object BAPR : SignalingSystemDriver {
}
override val parametersSchema = SigParametersSchema {}
override val isBlockDelimiterExpr = "!distant"
override val isRouteDelimiterExpr = "Nf"

override fun checkBlock(reporter: BlockDiagReporter, block: SigBlock) {
// Check that we have the correct number of signals
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@ object ETCS_LEVEL2 : SignalingSystemDriver {
override val parametersSchema = SigParametersSchema {}

override val isBlockDelimiterExpr = "true"
override val isRouteDelimiterExpr = "Nf"

override fun checkBlock(reporter: BlockDiagReporter, block: SigBlock) {
// Check that we have the correct number of signals
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@ object TVM300 : SignalingSystemDriver {
override val settingsSchema = SigSettingsSchema { flag("Nf") }
override val parametersSchema = SigParametersSchema {}
override val isBlockDelimiterExpr = "true"
override val isRouteDelimiterExpr = "Nf"

private fun maxSpeedForState(state: SigState): Speed {
return when (val aspect = state.getEnum("aspect")) {
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ object TVM430 : SignalingSystemDriver {
override val parametersSchema = SigParametersSchema {}

override val isBlockDelimiterExpr = "true"
override val isRouteDelimiterExpr = "Nf"

override fun checkBlock(reporter: BlockDiagReporter, block: SigBlock) {
// Check that we have the correct number of signals
Expand Down
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