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yosys

Here are 45 public repositories matching this topic...

efabless / caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad vexriscv openram sky130

Updated Feb 26, 2025
Verilog

efabless / caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad openram sky130

Updated Feb 22, 2022
Verilog

scarv / xcrypto

XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Jan 5, 2023
Verilog

yosys-f4pga-plugins

chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

toolchain fpga eda xilinx yosys xilinx-fpga yosys-plugin f4pga

Updated May 14, 2024
Verilog

mattvenn / fpga-sdft

sliding DFT for FPGA, targetting Lattice ICE40 1k

fpga verilog fourier fft icestorm yosys sdft

Updated Apr 24, 2020
Verilog

embedded-explorer / Open-Source-RTL-Design

This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop

vsd yosys gate-level-simulation open-source-rtl

Updated Jun 6, 2021
Verilog

risc8

osresearch / risc8

Mostly AVR compatible FPGA soft-core

microcontroller fpga yosys ice40 softcore upduino up5k

Updated Sep 30, 2021
Verilog

mmicko / enigmaFPGA

Enigma in FPGA

fpga verilog yosys ice40 blackice goboard

Updated May 18, 2019
Verilog

scarv / scarv-cpu

SCARV: a side-channel hardened RISC-V platform

open-source cryptography cpu crypto riscv verilog research-project mit-license ise formal-verification yosys instruction-set-architecture verilator riscv32 xcrypto

Updated Jan 11, 2023
Verilog

chili-chips-ba / openXC7-TetriSaraj

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

open-source gamedev fpga rtl xilinx soc verilog-hdl yosys basys3 tetris-game nextpnr xc7a35t

Updated Feb 23, 2025
Verilog

alangarf / tm1638-verilog

A basic verilog driver for the TM1638 LED and key matrix chip

verilog icestorm tm1638 yosys ice40 arachne-pnr

Updated Dec 22, 2017
Verilog

fayizferosh / yosys-tcl-ui-report

5 Day TCL begginer to advanced training workshop by VSD

linux bash open-source csv workshop tcl synthesis yosys shell-scripting vlsi-physical-design hardware-description-language static-timing-analysis tcl-programming tcl-extensions tcl-procedures opentimer eda-tools

Updated Oct 18, 2023
Verilog

DoctorWkt / ULX3S-Blinky

A blinky project for the ULX3S v3.0.3 FPGA board

fpga verilog yosys nextpnr prjtrellis

Updated Feb 16, 2019
Verilog

franzflasch / leiwand_rv32

RISC-V RV32I CPU written in verilog

fpga verilog qemu yosys risc-v ice40 rv32i oss-fpga

Updated Jul 11, 2020
Verilog

bnossum / midgetv

rv32i/rv32im/rv32imc for iCE40. Wishbone interface.

riscv verilog lattice microcode yosys ice40 wishbone rv32i verilator icebreaker ice40up5k upduino2 iceblink40-hx1k

Updated Oct 26, 2020
Verilog

romavis / lwdo-sdr-fw

LWDO-SDR firmware (FPGA & FTDI)

verilog sdr yosys ice40 nextpnr

Updated Mar 9, 2024
Verilog

avahidi / arm-foss

Experiment in creating an ARM Cortex-M0 SoC using only open source tools. This was just moved here from https://bitbucket.org/vahidi/arm-foss/

arm fpga yosys

Updated Jan 7, 2022
Verilog

Essenceia / MoldUPD64

RTL implementation of a MoldUPD64 receiver.

rtl verilog icarus-verilog formal-verification yosys itch ouch moldudp hft-network moldudp64

Updated Dec 7, 2023
Verilog

johnnycubides / digital-electronic-1-101

fpga verilog yosys iverilog ice40 cyclone-iv

Updated Feb 26, 2025
Verilog

scarv / xcrypto-ref

XCrypto: a cryptographic ISE for RISC-V

cryptography hardware riscv verilog ise formal-verification yosys risc-v

Updated Jun 27, 2019
Verilog

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